1. Field
Various embodiments of the present invention relate to a semiconductor device and an operating method thereof, and more particularly, to a semiconductor device capable of relieving a multi-bit error and an operating method thereof.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional semiconductor device 10.
The conventional semiconductor device 10 includes a data buffer 11 configured to transmit and receive data according to an external request and an Error-Correcting Code (ECC) block 12 configured to sense and correct an error of data read from a semiconductor memory device 1.
The ECC block 12 generates parity information corresponding to data when a write request is made, and stores the data and the generated parity information in a semiconductor memory cell array 2.
When a read request is made, the ECC block 12 determines whether or not there is an error in data from the semiconductor memory cell array 2. For this operation, the ECC block 12 uses the parity information stored with the data.
The ECC block 12 included in the conventional semiconductor device 10 may sense and correct a single-bit error when the single-bit error occurs. However, when a two or more-bit error occurs, the ECC block 12 may sense the error, but cannot correct the sensed error.